Nanometrics

Defect Inspection

Defects at a wafer level can have a highly harmful effect to the device yield. There are either surface defects which limit the growth of proper material on a substrate or reactor contamination affecting the electrical performance of a wafer – every defect can cause either low performance of a LED/transistor/diode or prevent the device from function. Early knowledge about defects can significantly improve yield, line performance and production output.

 

Nanometrics’ approach to defect inspection is different to conventional defect control. By using patented illumination and detection methods, the Imperia provides the information that matters: defects that affect device performance. The combination of surface defect inspection & PL based electrically active defects is outstanding by itself, providing this information at up to 100 wph in depended of the sample size allows production control without the need for wafer sampling strategies. Paired with Nanometrics’ proprietary RDE defect analysis and binning software suite, the user is able to monitor and optimize defect density and get an early indication about yield and performance.

 

PL Defect Map